1. Field of the Invention
The present invention relates in general back bias voltage generators, and more particularly to a back bias voltage generator for generating a voltage independent of a variation in an external voltage and regulating a back bias voltage according to the generated voltage so that the back bias voltage can be constant in level regardless of the variation in the external voltage.
2. Description of the Prior Art
Referring to FIG. 1, there is shown a block diagram of a conventional back bias voltage generator. As shown in this drawing, the conventional back bias voltage generator comprises a power-on signal generator 1 for generating a power-on signal PWRON at a time point that an external voltage Vcc is stabilized, a back bias voltage sensor 2 for generating an oscillation enable signal OSCEN in response to the power-on signal PWRON from the power-on signal generator 1, an oscillator 3 for generating an oscillating signal at a desired period in response to the oscillation enable signal OSCEN from the back bias voltage sensor 2, and a back bias voltage pump 4 for performing a voltage pumping operation in response to the oscillating signal from the oscillator 3 to generate a desired level of back bias voltage VBB and outputting the generated back bias voltage VBB to an external circuit and the back bias voltage sensor 2.
Referring to FIG. 2, there is shown a detailed circuit diagram of the power-on signal generator 1 in FIG. 1. As shown in this drawing, the power-on signal generator 1 includes a PMOS transistor PM1 having a source for inputting the external voltage Vcc, a drain connected to a ground terminal Vss through an NMOS transistor NM1 and a gate connected directly to the ground terminal Vss. The NMOS transistor NM1 acts as a capacitor.
The power-on signal generator 1 also includes a PMOS transistor PM2 having a drain connected to a node between the PMOS transistor PM1 and the NMOS transistor NM1, and a gate and a source connected in common to the ground terminal Vss through an NMOS transistor NM2. The NMOS transistor NM2 acts as a capacitor.
Further, the power-on signal generator 1 includes an inverter I1 having an input terminal connected to a node between the PMOS transistor PM2 and the NMOS transistor NM2, and an inverter I2 having an input terminal connected to an output terminal of the inverter I1 and for inputting the external voltage Vcc through a PMOS transistor PM3 and an output terminal for outputting the power-on signal PWRON to the back bias voltage sensor 2. The PMOS transistor PM3 acts as a capacitor.
Referring to FIG. 3, there is shown a detailed circuit diagram of the back bias voltage sensor 2 in FIG. 1. As shown in this drawing, the back bias voltage sensor 2 includes PMOS transistors PM11 and PM12 having sources for inputting the external voltage Vcc in common and drains connected in common, respectively, an NMOS transistor NM11 having a drain connected to the drain of the PMOS transistor PM11, and NMOS transistors NM12 and NM13 connected in series to a source of the NMOS transistor NM11. The PMOS and NMOS transistors PM11 and NM11 have gates connected in common to the ground terminal Vss, respectively. The NMOS transistor NM12 has a gate and a drain connected in common to the source of the NMOS transistor NM11. The NMOS transistor NM13 has a gate and a drain connected in common to a source of the NMOS transistor NM12.
The back bias voltage sensor 2 also includes an inverter I11 having an input terminal connected in common to the drains of the PMOS transistors PM11 and PM12 and an output terminal connected to a gate of the PMOS transistor PM12, an inverter I12 having an input terminal connected to the gate of the PMOS transistor PM12 and the output terminal of the inverter I11, an NMOS transistor NM14 having a source for inputting the external voltage Vcc through a PMOS transistor PM13, and an NMOS transistor NM15 having a source connected to the ground terminal Vss, a gate for inputting the external voltage Vcc through the PMOS transistor PM13 and a drain connected in common to a drain of the NMOS transistor NM14 and a source of the NMOS transistor NM13 and for inputting the back bias voltage VBB from the back bias voltage pump 4. The PMOS transistor PM13 acts as a capacitor.
Further, the back bias voltage sensor 2 includes a NAND gate ND11 having one input terminal connected to an output terminal of the inverter I12 and the other input terminal connected to a gate of the NMOS transistor NM14 and for inputting the power-on signal PWRON from the power-on signal generator 1, and an inverter I13 having an input terminal connected to an output terminal of the NAND gate ND11 and an output terminal for outputting the oscillation enable signal OSCEN to the oscillator 3.
The operation of the conventional back bias voltage generator with the above-mentioned construction will hereinafter be described with reference to FIGS. 4A to 7. FIGS. 4A to 4D are timing diagrams illustrating the operation of the conventional back bias voltage generator in FIG. 1, FIG. 5 is a graph illustrating a relationship between the external voltage Vcc and the back bias voltage VBB in FIG. 1, FIG. 6 is a sectional view illustrating a construction of a general transistor and FIG. 7 is a graph illustrating a relationship between the external voltage Vcc and a voltage Vpp used in FIG. 6.
First, in the power-on signal generator 1, the external voltage Vcc is supplied to the source of the PMOS transistor PM1 and then set up to a constant level after the lapse of a predetermined time period as shown in FIG. 4A. The predetermined time period corresponds to an RC time constant which is determined by the PMOS transistor PM1 acting as a resistor and the NMOS transistor NM1 acting as the capacitor.
At the moment that the external voltage Vcc is set up to the constant level, the power-on signal PWRON which is applied from the power-on signal generator 1 to the back bias voltage sensor 2 goes high in logic as shown in FIG. 4B.
On the other hand, in the case where the power-on signal PWRON from the power-on signal generator 1 is low in logic, the back bias voltage sensor 2 is operated in the following manner. The low logic power-on signal PWRON from the power-on signal generator 1 is applied to the NAND gate ND11 and the gate of the NMOS transistor NM14. As a result, the NAND gate ND11 outputs a high logic signal to the inverter I13 regardless of the state of the external voltage Vcc, thereby causing the oscillation enable signal OSCEN which is outputted from the inverter I13 to the oscillator 3 to become low in logic. Also, the NMOS transistor NM14 is turned off. As a result, the external voltage Vcc through the PMOS transistor PM13 is not transferred to the NMOS transistor NM14 but to the gate of the NMOS transistor NM15, thereby causing the NMOS transistor NM15 to be turned on. In result, the back bias voltage VBB becomes a ground level Vss.
Subsequently, the oscillator 3 outputs no oscillating signal to the back bias voltage pump 4 in response to the low logic oscillation enable signal OSCEN from the back bias voltage sensor 2. As a result, the back bias voltage pump 4 remains at its stop state.
When the power-on signal PWRON from the power-on signal generator 1 goes high in logic under the condition that the oscillation enable signal OSCEN from the back bias voltage sensor 2 is low in logic, the NMOS transistor NM14 in the back bias voltage sensor 2 is turned on.
Then in the back bias voltage sensor 2, a voltage at a node A becomes the state of the back bias voltage VBB or the ground level Vss because of the turning-on of the NMOS transistor NM14. After being released from the ground level Vss, the back bias voltage VBB is supplied to the gate of the NMOS transistor NM15 through the NMOS transistor NM14.
At this time, because the NMOS transistors NM11-NM13 remain at their OFF states, the input terminal of the inverter I11 becomes high in logic and the output signal from the inverter I12 goes high in logic.
Upon receiving the high output signal from the inverter I12 and the high power-on signal PWRON from the power-on signal generator 1, the NAND gate ND11 outputs a low logic signal to the inverter I13. As a result, the oscillation enable signal OSCEN from the inverter I13 goes high in logic as shown in FIG. 4C. The high oscillation enable signal OSCEN from the inverter I13 is supplied to the oscillator 3.
The oscillator 3 generates the oscillating signal at the desired period in response to the high oscillation enable signal OSCEN from the back bias voltage sensor 2 and outputs the generated oscillating signal to the back bias voltage pump 4. Upon receiving the oscillating signal from the oscillator 3, the back bias voltage pump 4 performs a negative (-) pumping operation for the back bias voltage VBB, thereby causing the back bias voltage VBB to be gradually lowered in level as shown in FIG. 4D. Then, the bias voltage pump 4 outputs the resultant back bias voltage VBB to the external circuit and the back bias voltage sensor 2.
At the moment that the back bias voltage VBB is lowered to -3V.sub.T, the NMOS transistors NM11-NM13 are turned on, thereby causing the input terminal of the inverter I11 to go low in logic and the output signal from the inverter I12 to become low in logic.
The NAND gate ND11 outputs a high logic signal to the inverter I13 because it inputs the low output signal from the inverter I12 and the high power-on signal PWRON from the power-on signal generator 1. As a result, the oscillation enable signal OSCEN from the inverter I13 goes low in logic as shown in FIG. 4C. The low oscillation enable signal OSCEN from the inverter I13 is supplied to the oscillator 3.
In response to the low oscillation enable signal OSCEN from the back bias voltage sensor 2, the oscillator 3 stops the generation of the oscillating signal. Because receiving no oscillating signal from the oscillator 3, the back bias voltage pump 4 stops the negative (-) pumping operation for the back bias voltage VBB, thereby causing the back bias voltage VBB to be constant in level. Then, the bias voltage pump 4 outputs the resultant back bias voltage VBB to the external circuit and the back bias voltage sensor 2.
By the way, in the conventional back bias voltage generator, the external voltage Vcc is directly supplied to the back bias voltage sensor 2. For this reason, an amount of current flowing through each of the PMOS transistors PM11 and PM12 is varied with a variation of the external voltage Vcc, resulting in a variation in trip voltages of the inverters I11 and I12 and the NAND gate ND11.
In result, the back bias voltage VBB is gradually lowered in level as the external voltage Vcc is increased in level, as shown in FIG. 5.
On the other hand, a memory device comprises generally circuits such as a word line driver, an output buffer and etc. using the voltage Vpp, which is higher than the external voltage Vcc. The circuits of the memory device include generally the transistor as shown in FIG. 6. As shown in FIG. 6, the transistor includes a P-type substrate to which the back bias voltage VBB is applied, and an N.sup.+ diffusion region having a drain for inputting the voltage Vpp, a gate for inputting a control signal and a source connected to the ground terminal.
However, under the condition that the external voltage Vcc is high in level as shown in FIG. 7, a high electric field is applied to a junction of the transistor in FIG. 6 because the back bias voltage VBB is lowered in level whereas the voltage Vpp becomes higher in level, resulting in a degradation in the reliability of the transistor.
As mentioned above, in the conventional back bias voltage generator, the back bias voltage VBB is gradually lowered in level whereas the voltage Vpp becomes higher in level as the external voltage Vcc is increased in level. As a result, the high electric field is applied to the junction of the transistor, resulting in the degradation in the reliability of the transistor.